The present invention relates generally to manufacture of flash memory devices, and more particularly, to an apparatus and method for providing margining voltages generated on-chip during testing of the CAM (content addressable memory) portion of a flash memory device.
The xe2x80x9cDetailed Descriptionxe2x80x9d section is organized with the following sub-sections:
A. BIST(Built-in-Self-Test) System;
B. BIST(Built-in-Self-Test) Interface;
C. Back-End BIST(Built-in-Self-Test) State Machine;
D. On-Chip Repair of Defective Address of Core Flash Memory Cells;
E. Diagnostic Mode for Testing Functionality of BIST (Built-in-Self-Test) Back-End State Machine;
F. Address Sequencer within BIST (Built-In-Self-Test) System;
G. Pattern Generator in BIST (Built-In-Self-Test) System;
H. On-Chip Erase Pulse Counter for Efficient Erase Verify BIST (Built-In-Self-Test) Mode; and
I. Generation of Margining Voltage On-Chip During Testing CAM Portion of Flash Memory Device.
The present invention relates to sub-section xe2x80x9cIxe2x80x9d entitled xe2x80x9cGeneration of Margining Voltage On-Chip During Testing CAM Portion of Flash Memory Devicexe2x80x9d, with particular reference to FIGS. 74-83.
Referring to FIG. 1, a flash memory cell 100 of a flash memory device includes a tunnel dielectric structure 102 typically comprised of silicon dioxide (SiO2) or nitrided oxide as known to one of ordinary skill in the art of integrated circuit fabrication. The tunnel dielectric structure 102 is disposed on a semiconductor substrate or a p-well 103. In addition, a floating gate structure 104, comprised of a conductive material such as polysilicon for example, is disposed over the tunnel dielectric structure 102. A dielectric structure 106, typically comprised of silicon dioxide (SiO2), is disposed over the floating gate structure 104. A control gate structure 108, comprised of a conductive material, is disposed over the dielectric structure 106.
A drain bit line junction 110 that is doped with a junction dopant, such as arsenic (As) or phosphorous (P) for example, is formed within an active device area 112 of the semiconductor substrate or p-well 103 toward a left sidewall of the floating gate structure 104 in FIG. 1. A source bit line junction 114 that is doped with the junction dopant is formed within the active device area 112 of the semiconductor substrate or p-well 106 toward a right sidewall of the floating gate structure 104 of FIG. 1.
During the program or erase operations of the flash memory cell 100 of FIG. 1, charge carriers are injected into or tunneled out of the floating gate structure 104. Such variation of the amount of charge carriers within the floating gate structure 104 alters the threshold voltage of the flash memory cell 100, as known to one of ordinary skill in the art of flash memory technology. For example, when electrons are the charge carriers that are injected into the floating gate structure 104, the threshold voltage increases. Alternatively, when electrons are the charge carriers that are tunneled out of the floating gate structure 104, the threshold voltage decreases. These two conditions are used as the two states for storing digital information within the flash memory cell 100, as known to one of ordinary skill in the art of electronics.
During programming of the flash memory cell 100 for example, a voltage of +9 Volts is applied on the control gate structure 108, a voltage of +5 Volts is applied on the drain bit line junction 110, and a voltage of 0 Volts is applied on the source bit line junction 114 and on the semiconductor substrate or p-well 103. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are injected into the floating gate structure 104 to increase the threshold voltage of the flash memory cell 100 during programming of the flash memory cell 100.
Alternatively, during erasing of the flash memory cell 100, a voltage of xe2x88x929.5 Volts is applied on the control gate structure 108, the drain bit line is floated at junction 110, and a voltage of +4.5 Volts is applied on the source bit line junction 114 and on the semiconductor substrate or p-well 103 for example. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are pulled out of the floating gate structure 104 to decrease the threshold voltage of the flash memory cell 100 during erasing of the flash memory cell 100. Such an erase operation is referred to as an edge erase process by one of ordinary skill in the art of flash memory technology.
In an alternative channel erase process, a voltage of xe2x88x929.5 Volts is applied on the control gate structure 108 and a voltage of +9 Volts is applied on the semiconductor substrate or p-well 103 with the drain and source bit line junctions 110 and 114 floating. With such bias, when the flash memory cell 100 is an N-channel flash memory cell, electrons are pulled out of the floating gate structure 104 to the substrate or p-well 103 to decrease the threshold voltage of the flash memory cell 100 during erasing of the flash memory cell 100.
FIG. 2 illustrates a circuit diagram representation of the flash memory cell 100 of FIG. 1 including a control gate terminal 150 coupled to the control gate structure 108, a drain terminal 152 coupled to the drain bit line junction 110, a source terminal 154 coupled to the source bit line junction 114, and a substrate or p-well terminal 156 coupled to the substrate or p-well 103. FIG. 3 illustrates an electrically erasable and programmable memory device 200 comprised of an array of flash memory cells, as known to one of ordinary skill in the art of flash memory technology. Referring to FIG. 3, the array of flash memory cells 200 includes rows and columns of flash memory cells with each flash memory cell having similar structure to the flash memory cell 100 of FIGS. 1 and 2. The array of flash memory cells 200 of FIG. 3 is illustrated with 2 columns and 2 rows of flash memory cells for simplicity and clarity of illustration. However, a typical array of flash memory cells comprising an electrically erasable and programmable memory device has more numerous rows and columns of flash memory cells.
Further referring to FIG. 3, in the array of flash memory cells 200 comprising an electrically erasable and programmable memory device, the control gate terminals of all flash memory cells in a row of the array are coupled together to form a respective word line for that row. In FIG. 3, the control gate terminals of all flash memory cells in the first row are coupled together to form a first word line 202, and the control gate terminals of all flash memory cells in the second row are coupled together to form a second word line 204.
In addition, the drain terminals of all flash memory cells in a column are coupled together to form a respective bit line for that column. In FIG. 3, the drain terminals of all flash memory cells in the first column are coupled together to form a first bit line 206, and the drain terminals of all flash memory cells in the second column are coupled together to form a second bit line 208. Further referring to FIG. 3, the source terminal of all flash memory cells of the array 200 are coupled together to a source voltage VSS, and the substrate or p-well terminal of all flash memory cells of the array 200 are coupled together to a substrate voltage VSUB.
Referring to FIG. 4, a flash memory device comprised of an array of flash memory cells as illustrated in FIG. 3 for example is fabricated on a semiconductor die of a semiconductor wafer 220. A plurality of semiconductor dies are manufactured on the semiconductor wafer 220. Each square area on the semiconductor wafer 220 of FIG. 4 represents one semiconductor die. More numerous semiconductor dies are typically fabricated on a semiconductor wafer than shown in FIG. 4 for clarity of illustration. Each semiconductor die of FIG. 4 has a respective flash memory device comprised of an array of core flash memory cells.
During manufacture of the flash memory devices on the semiconductor wafer 220, each flash memory device on a semiconductor die is tested for proper functionality, as known to one of ordinary skill in the art of flash memory device manufacture. Referring to FIG. 5, an example semiconductor die 222 has a flash memory device comprised of an array of core flash memory cells 224. Referring to FIGS. 3 and 5, during testing of the flash memory device on the semiconductor die 222, an external test system applies bias voltages on the array of core flash memory cells 224 via contact pads 226 of the semiconductor die 222 for testing the array of core flash memory cells 224.
Referring to FIGS. 3 and 5, patterns of programming and erasing voltages are applied on the array of core flash memory cells 224 by the external test system via the contact pads 226 according to a plurality of flash memory test modes. For example, the array of core flash memory cells 224 are programmed and erased in an alternating checker-board pattern in one test mode. Alternatively, the flash memory cells located in the diagonal of the array of core flash memory cells 224 are programmed in another test mode. Then, a read operation is performed on the array of core flash memory cells by the external test system for each test mode via the contact pads 226 to determine that the array of core flash memory cells 224 are properly programmed and erased. Such a plurality of flash memory test modes and such an external test system for testing the proper functionality of the array of core flash memory cells are known to one of ordinary skill in the art of flash memory device manufacture. An example of such an external test system is the model V3300, available from Agilent Technologies, Inc., headquartered in Palo Alto, Calif.
In addition, a stable source of margining voltage is desired for consistent results of testing the proper functionality of the flash memory cells of the CAM (content addressable memory) portion of a flash memory device.
Accordingly, in a general aspect of the present invention, program and erase margining voltages for testing the proper functionality of the flash memory cells of the CAM of a flash memory device are generated on-chip for a more stable source of the program and erase margining voltages.
In one embodiment of the present invention, in an apparatus and method for generating a margining voltage for biasing a gate of a CAM (content addressable memory) cell of a flash memory device fabricated on a semiconductor wafer, a high voltage source is provided with a voltage generator fabricated on the semiconductor wafer. A low voltage source is provided from a node coupled to the voltage generator fabricated on the semiconductor wafer. For example, the voltage generator for providing the high voltage source includes a charge pump and a voltage regulator fabricated on the semiconductor wafer, and the low voltage source is the ground node.
In addition, a first transistor is coupled to the high voltage source, and a second transistor is coupled to the low voltage source. A first resistor is coupled between the first transistor and an output node, and a second resistor coupled between the second transistor and the output node. The margining voltage is generated at the output node. The first resistor and the second resistor form a resistive voltage divider at the output node between the high voltage source and the low voltage source when the first transistor and the second transistor are turned on. A logic circuit turns on the first transistor and the second transistor when a first set of control signals indicate that program margining of the CAM cell during a BIST (built-in-self-test) mode is invoked. The first transistor, the second transistor, the first resistor, the second resistor, and the logic circuit are fabricated on the semiconductor wafer.
In another embodiment of the present invention, the logic circuit turns off the first transistor and turns on the second transistor such that the output node discharges to a voltage of the low voltage source when a second set of control signals indicate that erase margining of the CAM cell during a BIST (built-in-self-test) mode is invoked. In addition, the logic circuit turns on the first transistor and turns off the second transistor such that the output node charges to a voltage of the high voltage source when a third set of control signals indicate that program margining of the CAM cell during a manual mode is invoked. Furthermore, the logic circuit turns off the first transistor and turns on the second transistor such that the output node discharges to a voltage of the low voltage source when a fourth set of control signals indicate that erase margining of the CAM cell during a manual mode is invoked.
In a further embodiment of the present invention, the logic controller delays turning on the first transistor until the high voltage source is stabilized. In another embodiment of the present invention, a respective set of pass transistors is coupled to the output node for coupling the output node to a respective set of CAM cells.
In this manner, the program or erase margining voltages for testing the flash memory cells of the CAM are generated on-chip with a resistive divider coupled to a regulated high voltage source such that the margining voltages are more stable than the voltage VCC provided by the external test system. With more stable margining voltages, the results of testing the CAM of the flash memory device are more consistent across a high number of lots of semiconductor wafers. In addition, with such on-chip generated margining voltages that are independent of the VCC voltage from the external test system, the results of testing the CAM of the flash memory device are more consistent even when various levels of the VCC voltage from the external test system are used for testing the core flash memory cells.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.